library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity flopr is
    generic(n: integer);
    port(
    d : in std_logic_vector(n downto 0);
    clk, rst: in std_logic;
    q: out std_logic_vector(n downto 0)
    );
end flopr;

architecture behav of flopr is
begin
    process (clk, rst)
    begin
        if rst = '1' then
            q <= conv_std_logic_vector(0, n+1);
        elsif clk'event and clk = '1' then
            q <= d;
        end if;
    end process;
end behav;
